1. Field of the Invention
The present invention relates to a high-speed phase-locked loop (PLL) circuit. In particular, the present invention relates to the configuration of a PLL circuit applicable to a frequency synthesizer employed typically in a digital portable wireless telephone or other communication equipment and also relates to a high-speed PLL suitable for a high-speed frequency synthesizer capable of responding quickly to a change in desired value of the controlled frequency.
2. Description of the Related Art
As is generally known, a representative application of a PLL (Phase-Locked Loop) circuit is a PLL frequency synthesizer which works as a closed-loop control system comprising a phase comparator, a loop filter, a voltage-controlled oscillator (VCO) and a frequency divider.
With the portable telephone going digital, in the PHS (Personal Handy-Phone System) portable telephone, for example, there is demanded a high-speed PLL frequency synthesizer capable of switching 77 waves with different frequencies in the 1.9-GHz band with a bandwidth of 300 kHz from one to another in a time of the order of milliseconds or even microseconds.
As a technique of configuring a PLL frequency synthesizer embracing the conventional technology, in general, a technique whereby a filter known as a lag-lead filter is used is adopted. This technique is described in detail for example in a document called `Bell System Technical Journal`, May 1980, Pages 127 to 136. Characteristics of a PLL using a loop filter of a circuit disclosed in this document can not be said to be adequate when an application to the contemporary digital radio equipment is taken into account. This is because, normally, an attempt is made to increase the speed of the PLL by using the conventional technology starting with an assumed form of the configuration of a base circuit derived from the intuition and the experience of the design engineer. In this case, a technique is adopted whereby optimal values of elements constituting the configuration of the circuit are found from a numerical analysis carried out by using a computer. With such a technique, however, not only is increasing the speed to a maximum value impossible, but there is also no guarantee that optimal circuit constants can be found by using the numerical searching technique even if the form of the configuration of the base circuit is appropriate as long as the assumed form of the configuration of the base circuit itself can not be used to achieve a maximum speed. As a result, there is raised a problem that a PLL with a sufficiently high speed can not be realized.